`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2020/11/21 09:36:41
// Design Name: 
// Module Name: mealy_top
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module mealy_top(
    input rst_i,
    input clk_i,
    input set_i,
    input [7:0] data_i,
    output reg detect_o/*,
    output reg [7:0] led*/
    );
    
	wire clk_div;
	
	reg [2:0] status = 3'b0;
    reg [7:0] read_buf = 8'b0;
	
	divider_1khz DIVIDER(clk_i, clk_div);
	
	always @(posedge clk_div or posedge rst_i) begin
		if (rst_i==1'b1) begin
			status = 3'b0;
			detect_o = 'b0;
		end else if (set_i) begin
			status = 3'b0;
			read_buf = data_i;
			detect_o = 'b0;
		end else if (status==3'd0) begin
			case(read_buf[7])
			    1'b0: status = 'd1;
			    default: status = 'd0;
			endcase
		end else if (status==3'd1) begin
			case(read_buf[7])
			    1'b1: status = 'd2;
			    default: status = 'd1;
			endcase
		end else if (status==3'd2) begin
			case(read_buf[7])
			    1'b0: status = 'd3;
			    default: status = 'd0;
			endcase
		end else if (status==3'd3) begin
			case(read_buf[7])
			    1'b1: status = 'd4;
			    default: status = 'd1;
			endcase
		end else if (status==3'd4) begin
			case(read_buf[7])
			    1'b1: begin status = 'd0; detect_o = 'd1; end
			    default: status = 'd3;
			endcase
		end else begin
		    detect_o <= detect_o;
		end
		
		read_buf = read_buf << 1;
	end
    
endmodule